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| SES Series Low Capacitance ESD Protector Array SES5VSC70-6U ROHS Description SES5VSC70-6U are surge rated diode arrays designed to protect high speed data interfaces. This device has been specifically designed to protect sensitive components which are connected to data and transmission lines from overvoltage caused by ESD transients). The unique design incorporates surge rated, low capacitance steering diodes and a TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The internal TVS diode prevents over-voltage on the power line, protecting any downstream components. The low capacitance array configuration allows the user to protect four high-speed data or transmission lines. The low inductance construction minimizes voltage overshoot during high current surges. This device is optimized for ESD protection of portable electronics. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (15kV air, 8kV contact discharge). (electrostatic discharge), CDE (Cable Discharge Events), and EFT (electrical fast Feature Array of surge rated diodes with internal TVS Diode SC-70-6 Package Protects up to four I/O lines & power line Low capacitance (<2pF) for high-speed interfaces No insertion loss to 2.0GHz Low leakage current and clamping voltage Low operating voltage: 5.0V Solid-state silicon-avalanche technology Transient protection for data lines to IEC 61000-4-2(ESD) 15KV(air), 8KV(contact); IEC 61000-4-4 (EFT) 40A (5/50ns) Applications USB 2.0 USB OTG Monitors and Flat Panel Displays Displays Digital Visual Interface (DVI) High-Definition Multimedia Interface (HDMI) Gigabit Ethernet SIM Ports IEEE 1394 Firewire Ports ESD Protector 1 www.goodark.com SES Series Low Capacitance ESD Protector Array SES5VSC70-6U ROHS Electrical characteristics per line@25(unless otherwise specified) Parameter Reverse stand-off voltage Reverse Breakdown voltage Reverse Leakage Current Clamping Voltage Clamping Voltage note1 Symbol VRWM VBR IR VC VC Conditions Pin 5 to 2 It = 1mA Pin 5 to 2 VRWM = 5V T=25 Pin 5 to 2 IPP = 1A tP = 8/20s Any pin to 2 IPP = 6A tP = 8/20s Any pin to 2 VR=0V f = 1MHz Any I/O pin to pin 2 VR=0V f = 1MHz Between I/O pins Min. 6 Typ. Max. 5 2 15 25 Units V V A V V pF pF 2 1 Junction Capacitance Cj Note 1: I/O pins are pin 1, 3, 4, and 6 Absolute maximum rating @25 Rating Peak Pulse Power (tp=8/20s) Peak Pulse Current (tp=8/20s) Operating Temperature Storage Temperature Symbol Ppp IPP TJ TSTG Value 150 6 -55 to +150 -55 to +150 Units W A Typical Characteristics ESD Protector 2 www.goodark.com SES Series Low Capacitance ESD Protector Array SES5VSC70-6U ROHS Typical Characteristics ESD Protector 3 www.goodark.com SES Series Low Capacitance ESD Protector Array SES5VSC70-6U ROHS Application Information Device Connection Options for Protection of Four High-Speed Data Lines This device is designed to protect data lines by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 3, 4 and 6. Pin 2 should be connected directly to a ground plane. The path length is kept as short as possible to minimize parasitic inductance. The positive reference is connected at pin 5. The options for connecting the positive reference are as follows: 1. To protect data lines and the power line, connect pin 5 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. 2. In applications where the supply rail does not exit the system, the internal TVS may be used as the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). 3. In applications where complete supply isolation is desired, the internal TVS is again used as the reference and VCC is connected to one of the I/O inputs. An example of this configuration is the protection of a SIM port. The Clock, Reset, I/O, and VCC lines are connected at pins 1, 3, 4, and 6. Pin 2 is connected to ground and pin 5 is not connected. Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint. ESD Protector 4 www.goodark.com SES Series Low Capacitance ESD Protector Array SES5VSC70-6U ROHS Product dimension and pad size Revision ESD Protector Date 5 Changes www.goodark.com SES Series ESD Protector 1.0 2008-7-3 SES5V706LC - ROHS Revision History ESD Protector 6 www.goodark.com |
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